The present invention relates to the processing of semiconductor substrates. More particularly, the present invention relates to methods for improving etch results while etching through an aluminum-containing layer.
In semiconductor processing, devices such as component transistors may be formed on a semiconductor wafer or substrate, which is typically made of silicon. Metallic interconnect lines, which are typically etched from an aluminum-containing layer disposed above the substrate, may then be employed to couple the devices together to form the desired circuit.
To facilitate discussion, FIG. 1 illustrates a cross-section view of a layer stack 20, representing some of the layers formed during the fabrication of a typical semiconductor integrated circuit. Although a semiconductor integrated circuit (IC) is discussed herein to facilitate ease of understanding, the discussion herein also pertains to substrates employed to fabricate other electronic components, e.g., glass panels employed to fabricate flat panel displays. It should be noted that other additional layers above, below, or between the layers shown may be present. Further, not all of the shown layers need necessarily be present and some or all may be substituted by other different layers.
At the bottom of layer stack 20, there is shown a substrate 100. An oxide layer 102, typically comprising SiO.sub.2, may be formed above substrate 100. A barrier layer 104, typically formed of a titanium-containing layer such as Ti, TiW, TiN or other suitable barrier materials, may be disposed between oxide layer 102 and a subsequently deposited metallization layer 106. In the case of FIG. 1, barrier layer 104 represents a two-layer structure, which includes a Ti layer underlying a TiN layer. Barrier layer 104, when provided, functions to prevent the diffusion of silicon atoms from oxide layer 102 into the aluminum-containing layer.
Aluminum-containing layer 106 may represent a layer of pure aluminum or may represent a layer formed of one of the known aluminum alloys such as Al--Cu, Al--Si, or Al--Cu--Si. The remaining two layers of FIG. 1, i.e., an anti-reflective coating (ARC) layer 108 and an overlying photoresist (PR) layer 110, may then be formed atop aluminum-containing layer 106. The ARC layer 108, typically comprising another titanium-containing layer such as TiN or TiW, may help prevent light (e.g., from the lithography step that patterns the photoresist) from being reflected and scattered off the surface of the aluminum-containing layer 106.
Photoresist layer 110 represents a layer of conventional photoresist material, which may be patterned for etching, e.g., through exposure to ultraviolet rays. As will be apparent, the layers of particular interest to the present invention are aluminum-containing layer 106 and photoresist layer 110, with all other layers being optional. The layers of layer stack 20 are readily recognizable to those skilled in the art and may be formed using any of a number of suitable and known deposition processes, including chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), and physical vapor deposition (PVD) such as sputtering.
To form the aforementioned metallic interconnect lines, a portion of the layers of the layer stack, including aluminum-containing layer 106, may be etched using a suitable photoresist technique. By way of example, one such photoresist technique involves the patterning of photoresist layer 110 by exposing the photoresist material in a contact or stepper lithography system, and the development of the photoresist material to form a mask to facilitate subsequent etching. Using an appropriate etchant, the areas of the aluminum-containing layer that are unprotected by the mask may then be etched away using an appropriate etching source gas, leaving behind aluminum-containing interconnect lines or features. By way of example, a commonly employed etchant for plasma etching the aluminum layer is a mixture of Cl.sub.2 and BCl.sub.3.
To achieve greater circuit density, modern semiconductor devices are scaled with increasingly narrower etch geometries. As a result, the feature sizes, i.e., the width of the interconnect lines or the spacings (e.g., trenches) between adjacent interconnect lines, have steadily decreased. By way of example, while a line width of approximately 0.8 microns (.mu.m) is considered acceptable in a 4 megabit (Mb) dynamic random access memory (DRAM) IC, 256 Mb DRAM IC's preferably employ interconnect lines as thin as 0.25 microns or even thinner.
The ever shrinking etch geometries however present many challenges to process engineers. As features become smaller and the photoresist mask becomes progressively thinner, it becomes increasingly important to come up with etch processes that can yield satisfactory etch results. This is because the etch results from the prior art Cl.sub.2 /BCl.sub.3 etch process tend to degrade when the feature size decreases below a certain point.
By way of example, photoresist selectivity is an etch result that process engineers constantly strive to improve. Photoresist selectivity refers to the ability of a given etch process to discriminate between the target layer to be etched (the aluminum-containing layer in this case) and the photoresist mask. Photoresist selectivity is frequently expressed in terms of the etch rate through the target layer versus the etch rate of the photoresist mask. Photoresist selectivity is quite important since the photoresist mask employed in the fabrication of modem semiconductor devices is quite thin. If a chosen etch process has too low a photoresist selectivity, the photoresist mask may be worn away before the etch is completed, causing etch damage to occur in regions of the underlying aluminum-containing layer where no etching is intended.
Micromasking residue is another important etch result that needs attention. In general, it is desirable that the chosen etch process does not leave unwanted residues or etch byproducts on the surface of the substrate after etching. This is because the presence of the unwanted residue may interfere with subsequent processing steps and/or with the proper performance of the resultant semiconductor device. Another important etch parameter is the etch rate through the aluminum-containing layer. Since a higher aluminum etch rate is advantageous from a cost of ownership standpoint (i.e., the production cost per substrate), a higher aluminum etch rate is generally desirable.
Still another important etch result is the profile microloading. Profile microloading occurs because the etching that occurs in the narrow spacings may differ from one that occurs in the open field regions. This difference may cause the sidewall profile of features in the dense region to assume a different shape from the sidewall profile of features in the open field region. With reference to FIG. 2, for example, it is seen therein that profile microloading causes a sidewall 202 and a sidewall 206 in the open field region to assume a more tapered profile than the more vertical sidewall 204 in the dense region. In this example, FIG. 2 represents the result after the layer stack of FIG. 1 has been etched with the prior art Cl.sub.2 /BCl.sub.3 etchant source gas in a plasma processing chamber. Because profile microloading represents an aberration in the critical dimension of the etched features, it is generally desirable to minimize profile microloading. These and other etch results are representative of the etch results that process engineers constantly strive to optimize to meet the challenge of fabricating modern highly dense semiconductor devices.